1. Field of the Invention
Embodiments of the present invention relate generally to data processing and, more specifically, to implementing ECC protection in an on-chip L2 cache.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that serves as an intermediate point between an external memory (e.g., off-chip frame buffer memory or dynamic random access memory (DRAM) units) and internal clients of the memory subsystem (referred to herein as the “clients”). The L2 cache temporarily stores data that the clients are reading from and writing to the external memory.
Typically, when writing data to the external memory, the clients are not required to write the whole data word. Instead, the clients provide “byte enables” that indicate which bytes of the word are written and which bytes are not written. The L2 cache stores the byte enables along with the data. For example, when a client writes 32 bits (i.e., 4 bytes) of data to the external memory, the L2 cache stores the 32 bits of data and 4 bits of byte enables (one 1-bit byte enable per byte of data), resulting in a total storage requirement of 36 bits. The byte enables indicate that the byte stored in the L2 cache is “updated,” and the byte represents the most recently written value of the corresponding location in the external memory. A byte that is enabled indicates that the value must be written to the external memory so that the external memory gets the most recently written value. A byte that is not enabled does not need to be written to the external memory.
One problem with the L2 cache is that this type of memory is subject to bit errors that may corrupt the data stored in the cache, especially as the memory size increases. One approach to mitigating bit errors and reducing the incidence of corrupted and unusable data is to use an Error Correcting Code (ECC) for the cached data. For example, when data is written to the L2 cache, an ECC may be used to generate check bits that correspond to the data being stored in the L2 cache. The ECC check bits may then be stored and retrieved at a later time whenever the stored data is accessed. The check bits when combined with the stored data are used to detect if the data stored in the L2 cache is corrupted, and in some cases of data corruption, to allow the data to be corrected. A significant drawback to implementing an ECC for the L2 cache is that storing the ECC check bits requires additional die space and potentially additional hardware, making the implementation far less attractive.
As the foregoing illustrates, what is needed in the art is a technique for protecting data stored in the L2 cache against data corruption without incurring the costs of conventional ECC implementations.